Design and Development of Efficient Energy Systems. Группа авторов

vedicmultiplier 139 13442.07 86424.01 99866.08

Table 2.5 Time constraint of 8x8 vedic multiplier.

Pins	Type	Fan out	Load (fF)	Slew (ps)	Delay (ps)	Arrival (ps)
p[14]	out port				0	2637 R

An instance of an 8-bit VM named Vedic multiplier requires 139 cells in this project; there is an unwanted sub-threshold current which is leakage of power in 13422.07nW (Nano Watt). Dynamic power, a part of power that consumed while the inputs are active, obtained value is 86424.01 nW and the total power which is obtained for this 8x8 Vedic Multiplier is 99866.08 nW shown in Table 2.4.

Here pin p[14] defines that it is the last output pin of 8x8 Vedic Multiplier and type defines whether it is input port or output port. The longest path arrival time (AT) of signal is calculated as the latency for a signal to arrive at point of consideration, for this project is 2637 ps shown in Table 2.5.

      2.4.4 16-Bit Multiplier

The 16x16 Vedic Multiplier requires 666 cells to implement this project, and the area which is obtained by cells is 5967, and the net area is “zero” as shown in Table 2.6. The total area in which it is accomplished is 5967, and there is no wire load for this Vedic Multiplier.

16-bit multiplier needs 666 cells to implement. Here unwanted sub-threshold current which is leakage of power in 60576.57 nW. The dynamic power of 16-bit multiplier to complete product are 444556.31 nW and the total power obtained to 505132.87 nW as shown in Table 2.7.

Table 2.6 Cell area of 16x16 vedic multiplier.

Instance	Cells	Cell area	Net area	Total area	Wire load
16-bit VM	666	5967	0	5967	<none> (D)

Table 2.7 Power constraints of 16x16 vedic multiplier.

Instance	Cells	Leakage power (nW)	Dynamic power (nW)	Total power (nW)
16-bit VM	666	60576.57	444556.31	505132.87

Table 2.8 Time constraint of 16x16 vedic multiplier.

Pin	Type	Fanout	Load (fF)	Slew (ps)	Delay (ps)	Arrival (ps)
p[30]	out port				0	5476 R

Table 2.9 Comparison of multiplier architecture.

8-bit Multiplier	Leakage power (μW)	Dynamic power (micro μW)	Total power (μW)	Delay (ns)	Cell count	Cell area
Vedic Multiplier	13.44	86.42	99.86	2.637	139	1517
Booth Multiplier [21]	5.69	324.53	330.22	3.75	214	5115
Wallace Tree Multiplier [21]	5.6263	655.55	661.17	3.02	248	1470
Dadda Multiplier [21]	5.62	655.807	2661.47	2.56	266	1330

Here pin p[30] defines that it is the last output pin of 16x16 Vedic Multiplier and type defines whether it is input port