Electrical and Electronic Devices, Circuits, and Materials. Группа авторов

dielectric materials (Hetero structure Si/GaAs/GaAs) HfO2 (k ≈ 25) ZrO2 (k ≈ 24) Si3N4 (k ≈ 12) SiO2 (k ≈ 3.9) Vth (V) 0.5 0.5 0.7 0.75 SS(mV/decade) 34.25 34.27 40.65 44.25 ION(A/μm) 4.00 × 10^-6 3.90 × 10^-6 2.00 × 10^-7 2.00 × 10^-8 IOFF(A/μm) 1.00 × 10^-20 1.00 × 10^-19 1.00 × 10^-19 1.00 × 10^-19 ION/IOFF 4.00 × 10¹⁴ 3.90 × 10¹⁴ 2.0 × 10¹² 2.00 × 10¹¹

Ideally in off-state, there is no current flow in TFET, due to large tunneling width (λ). But in practical case, few charge particles pass the λ, in off-state condition, resulting in smaller IOFF current. But practically the magnitude of the off current in case of TFET is smaller than MOSFETs. On the other hand, when applied VGS sufficiently large, tunneling barrier λ, between source and channel reduce significantly and sufficient number of charge particles to pass from source to drain via channel, resulting in ION current. Interestingly, when applied VGS is negatively high, the tunneling barrier width between the channel and drain narrows, which induces tunneling current [17–22]. The particular state of TFET device is known as ambipolar state and the amount of current following in this state is known as ambipolar (Iamb), as shown in Figure 2.6. Figure 2.6 is dedicated for study of ambimiparity behaviour of DG -TFET, an unwanted conduction known as malfunction. Figure 2.6 shows the comparision of ambipolar property of homo and hetero structure DG - TFET. The result shows that, DG -TFET with adopted technology shows suppression of the ambipolar current (Iamb) without deteriorating analog, and transient performance. From Figure 2.6, it has been observed, with the help of 2-D. TCAD simulation that, the ambipolar current (Iamb) is suppressed by 10⁸ order of magnitude in proposed Si/GaAs/GaAs hetero DG - TFET as compared to Si/Si/Si homo DG -TFET up to the applied gate voltage of V_GS = − 3.0V the step of gate voltage was taken equal to 0.5V.

Figure 2.6 Comparision of ambipolar current vs. applied gate drive voltage (V_GS) for homo and hetero structure double gate tunnel FET.

Figure 2.7 shows the impact of drain voltage (VDS) on DG -TFET. From Figure 2.7, it is clearly evident that applied drain voltage (VDS) has negligible impact on TFET performance. This is strong evidence that TFET is almost free from DIBL (Drain Induced Barrier Lower). This is a strong recommendation for replacement of conventional low-power device, circuit and system with TFETs and TFET-based circuit and system design.

The transconductance (gm) represents amplification ability of device and important design parameter of circuit and system design. It is defined as the slope of the transfer characteristic. The gm value can be calculated by mathematical Equation 2.4. Figure 2.8 shows the variation of gm versus applied VGS. From Figure 2.8, it has been observed that g_m value decreases with decrease of applied gate voltage, VGS that is due smaller tunneling current at lower VGS.

Figure 2.7 Device transfer characteristics for double gate N- TFET hetero structure with a variation of V_DS plot (a) linear (b) Semilog.

Figure 2.8 Sensitivity of transconductance (gm) with applied gate voltage (VGS) and comperision between double gate hetero and homo structure DG -TFET.

Figure 2.9 shows 3D visualization of transconductance, cut-frequency and applied gate voltage (gm, f_T, VGS). From Figure 2.9 and Figure 2.10, clearly, it has been observed that the hetero and homo structures: transconductance, cut-frequency (gm, f_T) increase rapidly as external applied gate voltage V_GS increases. The maximum gm-hetero value of the hetero DG -TFET ~1.6 μS/μm and f_T-hetero ~ 0.65 GHz and gm-homo ~1.4 μS/μm f_T-homo ~ 0.55GHz. The gm-hetero > gm-homo due to smaller effective tunneling barrier width (i.e. λ _hetero ~ 0.05 µm< λ _hetero ~0 .056 µm), shown in Figure 2.2 and Figure 2.3

Figure 2.9 3D - transconductance (gm), cut-frequency (fT) and applied gate drive voltage (VGS) of hetero DG -TFET.