Multi-Processor System-on-Chip 1. Liliana Andrade

architecture, pervasive computing, ubiquitous computing

       PE6_10 Web and information systems, database systems, information retrieval and digital libraries, data fusion

      PE7 Systems and Communication Engineering

       PE7_2 Electrical engineering: power components and/or systems

      Foreword

       Ahmed JERRAYA

       Cyber Physical Systems Programs, CEATech, Grenoble, France

      Multi-core and multi-processor SoC (MPSoC) concepts started in the late 1990s, mainly to mitigate the complexity of application-specific integrated circuits (ASICs) and to bring some flexibility. The integration of instruction-set processors into ASIC design aimed both to structure the architecture and to allow for programmability. The concept was adopted for general-purpose CPU and GPU in the second phase. Among the pioneers of MPSoC design, we can list the MPA architecture from ST that used eight specific cores to implement MPEG4 in 1998. This evolved 10 years later to give rise to MPPA, the Kalray’s general-purpose MPSoC architecture. Another pioneer is the emotion engine from Sony that used five cores (two DSP and three RISC) to build the application processor for the PlayStation (PS2). This also evolved and later converged to bring the CELL architecture (developed jointly by Sony, IBM and Toshiba) in 2005. In 2000, Lucent announced Daytona (quad SPARC V8), and in 2001, Philips designed the famous Viper architecture that combined a MIPS architecture and a DSP (Trimedia). In 2004, TI introduced the OMAP architecture that combined an ARM and a DSP. Using MPSoC to build specific architectures is continuing, and almost every SoC produced today is a multi (or many) core architecture. An important evolution took place in 2005 with the ARM MPCore, the first general-purpose quad core. This was followed by several commercial, general-purpose multi-cores, including Intel Core Duo Pentium, AMD Opteron, Niagra Spark, the Cell processor (8 Cell cores + PowerPC, ring network).

MPSoC started a new computing era, but brought a twofold challenge: building multi-core HW that can be used easily by SW designers, and building distributed SW that fully exploits HW capabilities. To deal with these challenges, the design communities from Academia and Industry began a series of conferences and workshops to rethink classical distributed computing. The study of new methods, models and tools to deal with these new distributed HW and SW architectures generated new concepts, such as the interconnect architectures called network-on-chip (NoC). The MPSoC Forum, created in 2001, was the first interdisciplinary forum that brought together the leading thinkers from the different fields to design multi-core and multi-processor SoC. Over the last 20 years, MPSoC has been a unique opportunity for me to meet so many of the world’s top researchers and to communicate with them in person, in addition to enjoying the high-quality conference programs. The confluence of academic and industrial perspectives, and hardware and software, makes MPSoC not “yet another conference”. I have learned how emerging SW and HW design technologies and architectures can benefit from advanced semiconductor manufacturing technologies to build energy-efficient multi-core architectures that can serve advanced computing (image, vision and cloud) and distributed networked systems. This book, in two volumes (Architectures and Applications), was published to celebrate the 20th anniversary of MPSoC with outstanding contributions from previous MPSoC events.

      This first volume on architectures covers the key components of MPSoC: processors, memory, interconnect and interfaces.

      Acknowledgments

       Liliana ANDRADE and Frédéric ROUSSEAU

       Université Grenoble Alpes, CNRS, Grenoble INP, TIMA, 38000 Grenoble, France

      The editors are indebted to the MPSoC community who made this book possible. First of all, they acknowledge the societies that supported this project. EDAA and IEEE/CAS partially funded the organization of the first two events. Since its creation, IEEE/CEDA has sponsored the event. Industrial sponsors played a vital role in keeping MPSoC alive for the last 20 years; special thanks to Synopsys, Arteris, ARM, XILINX and Socionext. The event was created by a nucleus of several people who now form the steering committee (Ahmed Jerraya, Hannu Tenhunen, Marilyn Wolf, Masaharu Imai and Hiroto Yasuura). A larger group has, for the last 20 years, been working to form the community (Nicolas Ventroux, Jishen Zhao, Tsuyoshi Isshiki, Frédéric Rousseau, Anca Molnos, Gabriela Nicolescu, Hiroyuki Tomiyama, Masaaki Kondo, Hiroki Matsutani, Tohru Ishihara, Pierre-Emmanuel Gaillardon, Yoshinori Takeuchi, Tom Becnel, Frédéric Pétrot, Yuan Xie, Koji Inoue, Masaaki Kondo, Hideki Takase and Raphael David). The editors would like to acknowledge the outstanding contribution of the MPSoC speakers, and especially those who contributed to the chapters of this book. Finally, the editors would like to thank the people who participated in the careful reading of this book (Breytner Fernandez and Bruno Ferres).

PART 1 Processors

      1

      Processors for the Internet of Things

      Pieter VAN DER WOLF¹ and Yankin TANURHAN²

       ¹ Solutions Group, Synopsys, Inc., Eindhoven, The Netherlands

       ² Solutions Group, Synopsys, Inc., Mountain View, USA

      The Internet of Things (IoT) enables a “smart world” in which many billions of devices communicate to provide advanced functionalities. More specifically, a broad variety of IoT edge devices that can “sense”, “listen” and “see” is emerging to capture data for further processing and communication. Such devices have a broad range of compute requirements for implementing a mixture of control processing, digital signal processing (DSP), machine learning, security, etc. In this chapter, we analyze the compute requirements of IoT edge devices and discuss processor capabilities that support the efficient implementation of such devices. More specifically, we focus on IoT edge devices that demand low power consumption. We present concrete examples of versatile, configurable and extensible processors that provide capabilities for control processing, DSP (e.g. voice/audio processing, communications) and machine learning. The processor examples are complemented with benchmark data for illustrative IoT edge application functions.

1.1. Introduction

In recent years, computing paradigms have evolved significantly. One such paradigm is cloud computing, a centralized paradigm that aims to offer computing as a utility. Another complementary paradigm is edge computing, a decentralized paradigm that aims to offer smart compute capabilities at the edge of the network. A related term is the Internet of Things (IoT), which refers to large numbers of interconnected computing devices aimed at offering services to a great variety of applications.

      In this chapter, we specifically focus on IoT edge devices: smart devices at the edge of the network that interact with the “real world”. These devices acquire data from the environment using sensors. This data is subsequently processed locally on the IoT edge device and/or on computing devices in the network. For each application, a proper trade-off must be made about which functions to perform where based on the requirements for computing, bandwidth, latency, connectivity, security, reliability, etc.

      The number of IoT edge devices is predicted to grow to tens of billions over the coming years. Some example IoT edge devices are:

       – smartphones and tablets;

       –