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Figure 1.14 [10,31]. This planar fabrication technology consists of thermal oxidation of Si wafer to grow SiO₂ as the first step (a), second step (b) is the application of photoresist (PR) over SiO₂, third step (c) is the patterning of PR with the help of optical lithography, fourth step (d) is the etching out of SiO₂ and exposing selective surface of Si wafer, fifth step (e) is removal of the PR, sixth step (f) involves doping of impurity atoms selectively to produce p-n semiconductor junction, and the last step (g) is the metallization of the top layer and of the back side for electrical interconnects [10,31]. For the growth of high quality SiO₂, wet or dry thermal oxidation process can be used.

Figure 1.14 Schematic shows diagrammatically the various steps involved in fabrication of p-n junction diode. The first step (a) is the thermal oxidation for the growth of SiO₂ layer, second step (b) is the application of resist over the grown SiO₂ layer, third step (c) is the patterning of resist, fourth step (d) involves etching out SiO₂, fifth step (e) is the removal of the photoresist. After this, step (f) involves doping of foreign atoms by diffusion or ion-implantation and step (g) is the metallization step on the top layer and bottom side of the Si wafer for electrical contacts.

Dry oxidation is performed using dry oxygen for growing thinner oxide layers and produces high-grade features at Si-SiO₂ interface. Wet thermal oxidation takes place in presence of water vapour and is applied to grow thicker oxide layers because of its high growth rate in comparison to dry thermal oxidation. Growth of high-quality pin-hole free SiO₂ layer on Si wafer is an essential requirement in the production and monolithic integration of integrated circuitry (IC) [10,31]. High-quality SiO₂ layer works as device isolation material which prevents short-circuiting amongst various devices fabricated on a single Si wafer. It can also be used as a mask to define area covered under the junction in the fabrication of a semiconductor p-n junction [32-35]. As shown in Figure 1.14(b), an organic photoactive material called photoresist (PR) is applied uniformly over thermally grown dielectric oxide by a spin-coated at the suitable rounds per minute (rpm) of spinning [36,37]. PR adhesion on the wafer is improved through hardening the resist by evaporation of the solvent by baking the PR-spun wafer at 80°C - 90°C [31]. Next, the patterned mask is used to expose the wafer by illumination of UV-light [31]. A patterned mask is an optical mask or photomask used in optical lithography consisting of pattern of the integrated circuitry or IC. It is usually a glass substrate coated with the chrome (Cr) and a resist layer [38-40]. The opaque parts in an optical mask consist of Cr-metal coating responsible for the shadows casted during exposure of Si wafers. The exposed region of PR-spun wafer or the chemistry of the PR-spun part that is exposed to the radiation of UV-light changes according to the PR used as shown in Figure 1.14(c). A photoresist can be positive or negative depending on whether it softens or hardens on exposure to light [36,37,41]. The PR gets polymerized on exposure to light and it becomes difficult to remove it in an etchant. In the next step, the development process is followed by immersing the wafer in the developer solution [31,42]. Here, unexposed region or part of the PR-spun wafer that is not exposed to light because of falling under the opaque part of the optical mask dissolves in the developer solution and is washed away. On the other hand, the exposed region remains intact in the developer solution and is again baked under optimized time duration in the temperature range of 120°C-180°C. This not only improves the adhesion of the exposed part but also makes it robust for the next step of etching process to remove the oxide selectively. The unmasked oxide layer is removed by an etchant buffered hydrofluoric (BHF) acid as shown in step (d) of Figure 1.14. Finally, the PR is ashed-off by the physical process of plasma-asher utilizing oxygen (O₂) plasma [43,44] or through a chemical solution as shown in step (e) of Figure 1.14. As the last step of fabrication of p-n junction, diffusion or ion-implantation is performed as per the requirements as shown in step (f) of Figure 1.14, and followed by metallization for top and back contacts fabrication (step (g) of Figure 1.14). In step (f), solid-state diffusion process [10,18,31] dopes the opposite type of impurity or foreign atoms in high concentration into the oxide-layer free part of the relevantly doped substrate. For example, p-type of foreign atoms are doped in an n-type of substrate and vice-versa to form p-n junction. As a matter of fact, due to lateral straggle or distribution of implanted ions or lateral diffusion mechanisms [10,18,31], the width of the doped part is slightly larger than the unprotected area. Ion-implantation can be performed with a wide selection of masking materials inclusive of oxide, polysilicon, PRs and metals, low temperature process, such that, even organic materials like PRs can be used for masking, excellent lateral uniformity in addition to offering precise control of depth profile and doses [10,31,45]. After introduction of oppositely natured impurities in the substrate, top and back-contacts are deposited by sputtering, e-beam evaporation, thermal evaporation or even chemical vapour deposition forming the process of metallization [46-50]. This forms ohmic contacts and interconnects by depositing noble metals that include gold (Au), silver (Au) or even low cost metals, such as, copper (Cu) and nickel (Ni). Blanket deposition is required for metallization on the back-side of the wafer. Deposition is usually followed by low-temperature annealing for promoting adhesion and low-resistance interface between semiconductor and the metallic layer.

Crystalline silicon solar cell (c-Si)–based technology [51-57] has been recognized as the only environment-friendly viable solution to replace traditional energy sources for power generation. It is a cost-effective, renewable and long-term sustainable energy source. There have been constant efforts in reducing the manufacturing cost of solar panel technology, which is about three to four times higher in comparison to traditional carbon-based fuels [58-60]. In the manufacturing domain, fabrication of three basic c-Si solar cell configurations can be utilized, which are differentiated in the manner of generation of electron-hole (E-H) pairs on exposure to sunlight. The three basic c-Si solar cell configurations are monofacial [57,62-64] bifacial [65-69] and back-contacted [70,71] solar cell configurations as shown in Figure 1.15(a), 1.15(b) & 1.15(c).

In the monofacial solar cell configuration as shown in Figure 1.15(a), the top point contacts above the surface of antireflection (AR) film form metallic electrical contacts. On the other hand, the rear surface consists of completely covering thin metallized layer, which serves as the second electrode. This is the dominant configuration used in commercial manufacturing of c-Si solar panel technology. The bifacial solar cell consists of n-doped emitter on both top and rear sides of the p-type substrate such that both front and back surface metallic grids are similar as shown in Figure 1.15(b). Both top and bottom sides are capable of generating E-H pairs. The requirement of high efficiency of these solar cells is to have high lifetime of the minority carriers. In the third type shown in Figure 1.15(c), the back-contacted solar cell configuration, n/p floating junctions are formed on both sides such that p⁺-doped and n⁺-doped regions exist in each of the layers. In this geometry, the top surface does not consist of any metallic grid. The minority carrier lifetime in these types of solar cells should be high so that the E-H pairs can diffuse to the back-side of the cell and collectively form external current.