Quantum Computing. Hafiz Md. Hasan Babu

A B C _in Carry Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

      The output equations of the full-adder can be mapped with the quantum modified Thapliyal Srinivas gate (MTSG), as shown in figure 4.3, and the quantum full-adder can be obtained by putting D = 0, which is shown in figure 4.4. The quantum cost of the quantum full-adder is 6 and the delay is 5Δ.

      Figure 4.3. The quantum MTSG gate.

      Figure 4.4. The quantum MTSG gate as a quantum full-adder.

4.2 The quantum subtractor

      A subtractor is also an important logic component in circuit design. Subtractors are classified into two types: half-subtractors and full-subtractors. The half-subtractor circuit has two inputs A and B where the half-subtractor performs the A − B operation.

4.2.1 The quantum half-subtractor

      Table 4.3 is the truth table of a half-subtractor. From this table we can obtain the half-subtractor circuit:

      Difference=A⊕BBorrow=A¯B.

Table 4.3. The truth table of the half-subtractor.

A	B	Borrow	Difference
0	0	0	0
0	1	1	1
1	0	0	1
1	1	0	0

      The output equations of the half-subtractor can be mapped with a quantum Thapliyal Ranganathan (TR) gate, as shown in figure 4.5, and the quantum half-subtractor can be obtained by putting C = 0, which is shown in figure 4.6. The quantum cost of the quantum half-subtractor is 4 and the delay is 4Δ.

      Figure 4.5. The quantum TR gate.

      Figure 4.6. The quantum half-subtractor.

4.2.2 The quantum full-subtractor

      The full-subtractor circuit has three inputs A, B, and Cin, which realize the operation Y = A − B − C. Table 4.4 is the truth table of a full-subtractor. From this table we can obtain the output of the full-subtractor circuit:

      Difference=A⊕B⊕CinBorrow=(A⊕B¯)Cin⊕AB.

Table 4.4. The truth table of full-subtractor.

A	B	C in	Borrow	Difference
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	1	0
1	0	0	0	1
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

      A quantum full-subtractor can be designed using two quantum TR gates, shown in figure 4.7. Figure 4.8 is the optimized version of the full-subtractor. The quantum cost of a quantum full-subtractor is 6 and the delay is 4Δ.