Electronic Packaging Science and Technology. King-Ning Tu

mainframe compute...Figure 1.3 The petals of flower, which shows the required functions in 4G an...Figure 1.4 Scanning electron microscopy (SEM) image of the cross‐section of ...Figure 1.5 (a) Synchrotron radiation tomographic images of a similar device ...Figure 1.6 Schematic diagram of the cross‐section of a typical 3D IC device....Figure 1.7 An example of electromigration electromigration‐induced failure o...

      2 Chapter 2Figure 2.1 General process of packaging procedure with lead‐frame.Figure 2.2 Photo for lead‐frames.Figure 2.3 First and second bonds in ultrasonic wire bonding.Figure 2.4 General layout of tape circuit boards. Sprocket holes guide the t...Figure 2.5 Tape‐automated bonding procedure. Inner lead bonds connect die to...Figure 2.6 Schematic diagram of gang bonding. A press applies force to multi...Figure 2.7 Schematic diagram of flipping chip to form bonds at multiple sold...Figure 2.8 Schematic diagram of the cross‐section of a ceramic module joined...Figure 2.9 Schematic diagram of the cross‐section of a C4 flip‐chip solder j...Figure 2.10 Schematic diagram of the formation of a C‐4 solder joint of sold...Figure 2.11 Schematic diagram of automatic self‐alignment process in the ref...Figure 2.12 Schematic diagrams of the procedure in flip‐chip solder joint te...Figure 2.13 Schematic diagram of the distribution of C‐4 solder joint on the...Figure 2.14 Schematic diagram of the peripheral distribution I/O connections...Figure 2.15 Schematic diagram and SEM image of Cu/solder/Cu micro‐bump.Figure 2.16 SEM cross‐sectional image of side‐wall wetting and porous Cu₃Sn ...Figure 2.17 A plot of the I/O number per chip vs. various types of bonding t...Figure 2.18 Effect of surface roughness on minimum bonding temperature.Figure 2.19 Schematic diagram of the Cu‐to‐Cu interface. (a) The stress grad...Figure 2.20 The surface morphology of a Cu surface analyzed by atomic force ...Figure 2.21 (a) It shows the effect of surface roughness on the bonding time...Figure 2.22 Cross‐sectional TEM images of voids in the Cu‐to‐Cu bonding inte...Figure 2.23 (a) Plan‐view of TEM image of voids in the Cu‐to‐Cu bonding inte...Figure 2.24 Kagawa et al. presented their void distribution for the Cu‐to‐Cu...Figure 2.25 (a) A high‐resolution TEM image for a low‐angle grain boundary a...Figure 2.26 Cross‐sectional focus ion beam (FIB) and electron back‐scatter d...Figure 2.27 A plot of shear strength against bonding temperature of Cu pilla...Figure 2.28 Schematic diagrams depict the effect of Cu dishing on hybrid bon...Figure 2.29 Cross‐sectional SEM image of Cu interconnects with a pitch of ap...Figure 2.30 It shows state‐of‐the‐art of hybrid Cu‐to‐Cu bonds using the SiC...Figure 2.31 It shows the microstructures for a Cu‐to‐Cu joint after 1000 cyc...

      3 Chapter 3Figure 3.1 High resolution TEM images showing the atom migration under elect...Figure 3.2 Schematic diagram of the periodic nanotwin structure by repetitio...Figure 3.3 Biaxial stress in the model of calculation.Figure 3.4 (a) Calculated curves showing the evolution of the total energies...Figure 3.5 Schematic diagram depicts the in situ stress measurement system. ...Figure 3.6 The evolution of the product of stress and film thickness as a fu...Figure 3.7 Microstructures of pulsed electrodeposited randomly oriented nt‐C...Figure 3.8 The schematic drawing for dislocation slip between two parallel t...Figure 3.9 (a) FIB images of the both the top view and cross‐sectional view ...Figure 3.10 Plan‐view EBSD showing the orientation of surface grains of the ...Figure 3.11 Cross‐sectional FIB image of an electroplated [111]‐oriented nan...Figure 3.12 Grain growth in [111] nt‐Cu film. Cross‐sectional FIB images for...Figure 3.13 Transformation of the oriented (111) nt‐Cu to large grain (100) C...Figure 3.14 The growth of large (100) grains from the oriented (111) nt‐Cu. ...Figure 3.15 (a) Cross‐sectional EBSD orientation image map for a SnAg micro‐...Figure 3.16 Microstructures after solid‐state aging of nt‐Cu/solder/nt‐Cu at...Figure 3.17 Cross‐sectional FIB image showing the microstructures of nt‐Cu f...Figure 3.18 Schematic diagram of a void in the bonding interface. Under ther...Figure 3.19 Microstructures analysis of the bonding interface for a [111] nt...Figure 3.20 Schematic drawing for a fanout package. A chip is embedded in ep...Figure 3.21 Tensile stress and strain curves for regular Cu and nt‐Cu films ...Figure 3.22 Plot of yield strength against electrical and thermal conductivi...Figure 3.23 Voids and oxidation formation in the nt‐Cu line after current st...

      4 Chapter 4Figure 4.1 (a) A circular solder mount or cap on a copper substrate. (b) The...Figure 4.2 A schematic diagram of the cross‐section on an array of hemispher...Figure 4.3 The physical meaning of C^b and C^e are, respectively, the equilibr...Figure 4.4 A plot of φ(η) versus η.Figure 4.5 In a sample having a very thin layer of Sn, when the Sn was compl...Figure 4.6 SEM image of the opposite rows of IMC in a micro‐bump solder join...Figure 4.7 (a) After reflow at 260 C for four minutes of the same SnAg solde...

      5 Chapter 5Figure 5.1 The growth of a single IMC phase, the “i” phase, between two term...Figure 5.2 Free energy diagram of A (α‐phase) and B (β‐phase), and an IMC (i...Figure 5.3 SEM image of the distribution of Kirkendall voids in the layer of...Figure 5.4 A set of SEM cross‐sectional images of micro‐bumps after annealin...Figure 5.5 A schematic diagram of cellular precipitation is shown. The cell ...Figure 5.6 A schematic diagram of the growth of porous Cu₃Sn is shown, where...Figure 5.7 The pillar‐type samples are shown having various diameters, from ...Figure 5.8 SEM images of 1 1 μm pillars after annealing at 195 °C for (a) 30...Figure 5.9 (a and b) The change of IMC thickness with different diameters wh...Figure 5.10 The mechanism of Cu interstitial diffusion into 1 μm pillar is d...

      6 Chapter 6Figure 6.1 IC design style: full‐custom.Figure 6.2 IC design style: standard cell (row‐based).Figure 6.3 IC design style: field programmable gate array (FPGA).Figure 6.4 VLSI design process and flow.Figure 6.5 Evolution of minimum feature sizes in semiconductor manufacturing...Figure 6.6 Wire bonding