Electronic Packaging Science and Technology. King-Ning Tu

      

      Table of Contents

      1  Cover

      2  Title Page

      3  Copyright Page

      4  Preface

      5  1 Introduction 1.1 Introduction 1.2 Impact of Moore’s Law on Si Technology 1.3 5G Technology and AI Applications 1.4 3D IC Packaging Technology 1.5 Reliability Science and Engineering 1.6 The Future of Electronic Packaging Technology 1.7 Outline of the Book References

      6  Part I: 2 Cu‐to‐Cu and Other Bonding Technologies in Electronic Packaging 2.1 Introduction 2.2 Wire Bonding 2.3 Tape‐Automated Bonding 2.4 Flip‐Chip Solder Joint Bonding 2.5 Micro‐Bump Bonding 2.6 Cu‐to‐Cu Direct Bonding 2.7 Hybrid Bonding 2.8 Reliability – Electromigration and Temperature Cycling Tests Problems References 3 Randomly‐Oriented and (111) Uni‐directionally‐Oriented Nanotwin Copper 3.1 Introduction 3.2 Formation Mechanism of Nanotwin Cu 3.3 In Situ Measurement of Stress Evolution During Nanotwin Deposition 3.4 Electrodeposition of Randomly Oriented Nanotwinned Copper 3.5 Formation of Unidirectionally (111)‐oriented Nanotwin Copper 3.6 Grain Growth in [111]‐Oriented nt‐Cu 3.7 Uni‐directional Growth of η‐Cu₆Sn₅ in Microbumps on (111) Oriented nt‐Cu 3.8 Low Thermal‐Budget Cu‐to‐Cu Bonding Using [111]‐Oriented nt‐Cu 3.9 Nanotwin Cu RDL for Fanout Package and 3D IC Integration Problems References 4 Solid–Liquid Interfacial Diffusion Reaction (SLID) Between Copper and Solder 4.1 Introduction 4.2 Kinetics of Scallop‐Type IMC Growth in SLID 4.3 A Simple Model for the Growth of Mono‐Size Hemispheres 4.4 Theory of Flux‐Driven Ripening 4.5 Measurement of the Nano‐channel Width Between Two Scallops 4.6 Extremely Rapid Grain Growth in Scallop‐Type Cu6Sn5 in SLID Problems References 5 Solid‐State Reactions Between Copper and Solder 5.1 Introduction 5.2 Layer‐Type Growth of IMC in Solid‐State Reactions 5.3 Wagner Diffusivity 5.4 Kirkendall Void Formation in Cu₃Sn 5.5 Sidewall Reaction to Form Porous Cu₃Sn in μ‐Bumps 5.6 Effect of Surface Diffusion on IMC Formation in Pillar‐Type μ‐Bumps Problems References

      7  Part II: 6 Essence of Integrated Circuits and Packaging Design 6.1 Introduction 6.2 Transistor and Interconnect Scaling 6.3 Circuit Design and LSI 6.4 System‐on‐Chip (SoC) and Multicore Architectures 6.5 System‐in‐Package (SiP) and Package Technology Evolution 6.6 3D IC Integration and 3D Silicon Integration 6.7 Heterogeneous Integration: An Introduction Problems References 7 Performance, Power, Thermal, and Reliability 7.1 Introduction 7.2 Field‐Effect Transistor and Memory Basics 7.3 Performance: A Race in Early IC Design 7.4 Trend in Low Power 7.5 Trade‐off between Performance and Power 7.6 Power Delivery and Clock Distribution Networks 7.7