Soft-Switching Technology for Three-phase Power Electronics Converters. Rui Li

Actually, the voltage and the current of the power device have an overlap time during the switching transient process, which causes switching losses. The average switching loss is proportional to the switching frequency. To get an expected conversion efficiency, the switching frequency of inverters needs to be restricted. This type of converter is called hard‐switching converter. Hard‐switching converters can operate only at lower switching frequency. Lower switching frequency operation in turn results in bulkier passive components and higher audible noise. The wall to prevent the switching frequency from increasing is due to the switching loss. Can we reduce the switch loss of the inverter so that it can operate at higher switching frequency? To realize this goal, a technology to shape voltage and current of the power device during switching transient process, known as soft‐switching, occurs. Before a power device in a converter changes its status, either from on‐state to off‐state or from off‐sate to on‐state, the voltage across it or the current through it is set to zero with the help of the resonance between inductance and capacitance in the circuit. Soft‐switching is able to reduce the switching loss of the power semiconductor devices so that the converter can operate at higher switching frequency.

1.2 Concept of Soft‐switching Technique

A power device undergoes a switching transient process during its turn‐on as shown in Figure 1.8. From time t₁ to t₂, both voltage u_S1 across the device S₁ and current i_S1 through it have high values during turn‐on transient process. The voltage and current overlap on the device occurs during switch turn‐on process, which results in turn‐on loss. The turn‐on loss E_on is equal to integral of multiplication of the voltage u_S1 across the device S₁ and the current i_S1 through it in the turn‐on transient duration. Similarly, when the device turns off, it also undergoes a turn‐off transient process. The voltage and current overlap on the device occurs in the switch turn‐off process, which results in turn‐off loss E_off.

To reduce the turn‐on and turn‐off loss of the power device, soft‐switching techniques occur. The soft‐switching technique is a way to shape voltage and current of the power device during switching transient process by changing converter topology and/or introducing a unique control. Thus the overlapping of voltage and current on the power device during switching commutations is reduced. It not only reduces switching loss but also suppresses voltage stress on the power devices and electromagnetic interference (EMI) noise.

Figure 1.8 Typical switching waveforms of a power device.

      1.2.1 Soft‐switching Types

      Soft‐switching techniques are realized with innovated converter topologies and/or by introducing a unique control. There are many soft‐switching converter topologies and their control methods. Soft‐switching techniques can be summarized as four types as follows.

Zero‐Voltage‐Switching Turn‐on (ZVS‐on): During a power semiconductor device turn‐on process, voltage applied on the power device decreases almost to zero before the gate drive signal jumps to the high level for turning on the device. Thus the voltage and current overlapping of the device during turn‐on transient process is eliminated. As shown in Figure 1.9, voltage u_S1 on the device S₁ is set to zero before its gate drive signal u_g1 goes to the high level. Typically, a diode is antiparalleled with device S₁. Once voltage u_S1 on the device S₁ decreases to zero, the antiparalleled diode D₁ will conduct. It creates zero voltage turn‐on condition for the device S₁. Thus the overlapping of voltage and current of the power device during turn‐on process is got rid of. The integral of multiplication of u_S1 and i_S1 during turn‐on process becomes zero. Thus turn‐on loss of the device is avoided. ZVS‐on is ideal turn‐on process since it has no turn‐on loss.

Zero‐Current‐Switching Turn‐on (ZCS‐on): During a power device turn‐on process, its current gradually increases from zero value while its voltage quickly goes down. Thus the voltage and current overlapping of the device during turn‐on transient process is reduced. As shown in Figure 1.10, when gate drive signal steps up, the current i_S1 of the device gradually increases from zero value while the voltage quickly goes down. Typically, there is external inductor serially connected with the power device, which creates zero current turn‐on condition for the device S₁. Thus the overlapping of voltage and current of the power device during turn‐on process is reduced. The integral of multiplication of u_S1 and i_S1 during turn‐on duration becomes smaller than that of the hard switch. Thus turn‐on loss of the device is reduced. However, ZCS‐on is not ideal turn‐on process because turn‐on loss still exists. It still has the overlapping of the voltage and current in turn‐on transient process.

Figure 1.9 Zero‐voltage‐switching turn‐on.

Figure 1.10 Zero‐current‐switching turn‐on.

Zero‐Voltage‐Switching Turn‐off (ZVS‐off): During a power device turn‐off process, its voltage gradually increases from zero value while its current quickly goes down. Thus the voltage and current overlapping of the device during turn‐off transient process is reduced. As shown in Figure 1.11, when gate drive signal steps down for turning off the device, the voltage u_S1 of the device gradually increases from zero while the current i_S1 quickly goes down. Typically, there is capacitance paralleled with the power device, which suppresses the voltage increasing rate when the device turns off. Thus the overlapping of voltage and current of the power device during turn‐off process is reduced. The integral of multiplication of u_S1 and i_S1 during turn‐off process becomes smaller. Thus turn‐off loss of the device is reduced. However, ZVS‐off is also not ideal. There still exists turn‐off loss.

Zero‐Current‐Switching Turn‐off (ZCS‐off): Current through a power device already decreases to zero before the gate drive signal steps down to the lower level for turning off the device. Thus the voltage and current overlapping of the device during turn‐off transient process is eliminated. As shown in Figure 1.12, current i_S1 through the power device S₁ is set to zero before its gate drive signal u_g1 goes to the low level for turning off the device. Typically, there is an external inductor or L‐C resonance branch serially connected with the power device S₁, which causes the current of the device S₁ decrease to zero automatically before the turn‐off signal is applied to the gate drive. Thus the overlapping of voltage and current of the power device during turn‐off process is eliminated. The integral of multiplication of u_S1 and i_S1 in turn‐off duration becomes zero. Thus turn‐off loss of the device is avoided. ZCS‐off is ideal turn‐off.